Summary of Key Points
At the 2026 ISCAS conference, Huawei introduced the "Tao Law," which breaks away from the semiconductor industry's obsession with nanometer sizes and emphasizes that the essence of Moore's Law lies in "faster performance" rather than "smaller chips." The Tao Law aims to improve chip performance by optimizing signal delays at four levels: transistors, circuits, chips, and systems, thereby reducing what is referred to as the "time tax." Huawei has already used this approach to design 381 different chips, and this year, its Kirin chips will be the first to commercially utilize this technology on a large scale. However, implementing this technology requires significant barriers; only full-stack giants like Huawei and NVIDIA have the capability to fundamentally reinvent the underlying architecture. Most manufacturers can only partially adopt these methods, which also drives advancements in related industries such as packaging and EDA (Electronic Design Automation), providing new opportunities for China's semiconductor industry to make breakthroughs.
I. Tao Law: Moving Beyond the Nanometer Race to Achieve Better Performance
In the past, the semiconductor industry focused on improving performance by reducing transistor sizes (following Moore's Law). However, at the 7nm milestone, three major issues emerged: the cost of production equipment (EUV), the problem of increased quantum leakage due to extremely small transistors, and a diminishing return on performance improvements as chip sizes continued to shrink.
Huawei's Tao Law proposes a different approach: improving performance does not necessarily mean making chips smaller; instead, it focuses on reducing signal delays within the chip and throughout the system. This is achieved through a four-tier optimization framework:
- Device Layer: Optimizing the response speed of transistors themselves.
- Circuit Layer: Ensuring that signals travel shorter distances within the circuits.
- Chip Layer: Using "logic folding" technology to stack multiple layers of chips and connect them vertically, instead of using traditional flat wiring, thereby shortening signal paths.
- System Layer: Utilizing unified buses and optical interconnects to improve data transfer between chips and servers, addressing issues such as idle computing power and slow data movement.
This year's Kirin chips will incorporate logic folding technology, with impressive results: transistor density has increased from 155MTr/mm² to 238MTr/mm² (equivalent to an "effective 1.4nm" density), resulting in a 41% increase in energy efficiency and a 40% boost in operating speed.
II. Logic Folding vs. Traditional 3D Stacking: The Difference
Many people confuse logic folding with traditional 3D stacking, but there is a fundamental difference:
- Traditional 3D Stacking (False 3D): Chips are divided into larger modules (e.g., CPU, cache, storage), each made as a separate chip and then stacked together. The internal design of these modules remains flat. For example, AMD's 3D V-Cache optimizes the bandwidth between modules, not the internal delays.
- Huawei's Logic Folding (True 3D): Modules are broken down into smaller components, with circuits within the same module distributed across multiple layers of silicon wafers. Vertical connections are used instead of long flat wires, fundamentally reducing signal delays. The design considers all layers as a unified whole.
In simple terms, traditional 3D stacking is like building with large blocks, while Huawei's logic folding is like cutting the cake into smaller pieces and stacking them vertically, resulting in better performance but more complex technology.
III. High Barriers to Implementation: Only Full-Stack Giants Can Compete
Although the Tao Law is a promising approach, not everyone can adopt it:
- Most Manufacturers Lack Comprehensive Capabilities: Many chip companies focus on producing single chips (e.g., MCUs) and rely on off-the-shelf IP (pre-made circuit modules) and DDR standards (storage interfaces), limiting their ability to reinvent the underlying architecture.
- Differentiation in Implementation Levels:
- Full-Stack Giants (Huawei, NVIDIA): These companies can develop from chip design to end products entirely and directly apply the Tao Law to restructure the entire system.
- Smaller Manufacturers: They can only make partial optimizations, such as improving internal chip circuits, without altering the underlying architecture.
- General-Purpose Chips (e.g., Low-End MCUs): Their performance requirements are lower, so traditional technologies are sufficient, and they do not need logic folding.
This is similar to the transition from fuel-powered vehicles to electric cars; although the direction is correct, there are many supply chain and toolchain barriers, making it a decade-long process.
IV. Driving Industry Upgrades
The Tao Law also drives advancements in related industries:
- Packaging and Testing: Companies like Changjiang Technology and Tongfu Microelectronics need to invest in "ultra-fine pitch hybrid bonding" production lines for logic folding.
- EDA Tools: Domestic manufacturers such as Huada Jiutian must develop tools that support true 3D design, as current tools only handle 2D or false 3D.
- Optical Interconnects: Chinese companies are developing high-density optical modules based on Huawei's Hi-ONE technology to improve data transfer speeds between servers.
These developments will accelerate breakthroughs in key areas of China's semiconductor industry, such as packaging and EDA.
V. The Significance of the Tao Law: A New Path for China's Semiconductor Industry
While the world is still focused on nanometer sizes, Huawei has shown a new way forward by emphasizing performance improvements over size. Although this path is long and requires verification and collaboration from the entire industry chain, its significance lies in:
- Breaking the Foreign-Dominated Nanometer Race: It provides China with its own technological direction for semiconductor development.
- Proven Feasibility: The success of 381 different chips designed using this approach further validates its effectiveness.
- Potential as a Milestone: This could mark a significant breakthrough for China's semiconductor industry, shifting the focus from "how small the chip is" to "how fast it can perform."
For the first time, "time" has become an important factor in evaluating semiconductor performance.