Summary of Key Points
He Tingbo, the head of Huawei's semiconductor division, and his team have proposed the "Time Compression (τ-law)" theory as an alternative to the chip development approach that has relied on reducing transistor sizes for decades. This new theory aims to enhance performance, energy efficiency, and integration by compressing the time it takes for signals to propagate within chips. The V2 version of the paper, released in July, includes a substantial amount of empirical data and engineering details compared to the V1 version. It clarifies the evolution paths for Huawei's Kirin processors and Ascend AI platforms and extends these concepts to AI cluster systems. The team emphasizes that this is an engineering initiative that requires collaboration across the entire supply chain, rather than being achievable by a single company.
From "Smaller Chips" to "Faster Signals": What Exactly is the τ-law?
In the past, chip development focused on "geometric scaling"—making transistors progressively smaller, such as from 14nm to 7nm to 3nm—so that more transistors could be fitted onto a chip, resulting in improved performance. However, we are now approaching physical limitations (for example, the size of atoms), making this path unsustainable.
The τ-law offers a different approach: instead of focusing on reducing size, it emphasizes minimizing the time it takes for signals to travel within chips. The symbol "τ" represents the time constant for signal propagation. By employing techniques such as "logical folding" (stacking chip layers to reduce signal detours), "unified buses" (to improve communication between components), and "optical interconnections" (which transmit signals at the speed of light, faster than electrical signals), it is possible to enhance performance and energy efficiency while still integrating more functions.
The V2 Version: A Critical Step from Theory to Practice
While the V1 version primarily explained what the τ-law is, the V2 version addresses how to implement it, providing many practical details for engineers:
1. The introduction of the "gear ratio" concept: This refers to the spacing between layers in chip bonding techniques; it should be similar to the spacing of the metal wiring on top of the layers (with a ratio lower than 3, ideally closer to 1). Just as two gears of similar size work more smoothly together, this ensures that chip design software (EDA) can optimize multiple stacked layers as a cohesive whole, unlocking their full potential.
2. Additional insights into thermal management and design methods: Stacked chips generate heat, so the V2 version includes empirical data on "thermal sensing design" to help in controlling temperatures and preventing overheating.
3. More engineering verifications: For example, it shows how moving TSV (Vertical Through-Silicon Vias) from the top metal layer to the M6 layer can free up 30% of routing space—similar to moving wires from the ceiling to the middle of a wall in a house to create more room.
The Real Power of the Kirin Processors: Proving the τ-law
The V2 version uses data from Huawei's Kirin processors to demonstrate that the τ-law is not just theoretical:
- Clear roadmap: Kirin processors will evolve from two-layer stacks to three-layer and four-layer configurations, with Ascend990 AI chips expected to utilize logical folding around 2030.
- Empirical evidence: Comparing the Kirin2026 and Kirin9030 Pro, it shows that at the same performance level, the voltage required by Kirin2026 has been reduced from 1.1V to 0.9V, resulting in a 41% decrease in power consumption (from 100% of battery life for one hour of gaming to only 59%). Power density has also decreased by 5.6%, indicating that the τ-law can indeed make chips more energy-efficient and cooler without relying on more advanced manufacturing processes.
From Single Chips to AI Clusters: Solving the Bottleneck of Large Models
Large models like ChatGPT require multiple chips working together, but the current challenge is that even the strongest single-chip performance can be hindered by slow communication between chips, as well as between storage and computing components. The τ-law extends these concepts to entire AI systems:
- Collaboration of three key technologies: Unified buses for efficient interchip communication, Hi-ONE optical interconnections for fast data transfer, and 3D folding for faster internal chip interactions all help to balance the speed of computation, interconnection, and storage.
- System-level optimization: By designing the entire AI infrastructure as a cohesive whole, data flow can be optimized, thereby improving the training and inference speeds of large models.
It's Not Just Huawei: The Whole Supply Chain Needs to Work Together
He Tingbo emphasizes that the τ-law is not a mature solution but requires collaboration from the entire industry:
- Overcoming challenges: Chip design software (EDA) must adapt to three-dimensional stacking, manufacturing processes need to compensate for deviations, and new performance testing standards and business models are needed. None of these can be achieved by Huawei alone.
- The future landscape: He Tingbo hopes that within the next 6-10 years, companies and teams focused on the τ-law will lead the computing industry. This will require cooperation among chip manufacturers, software tool providers, wafer factories, and AI companies.
With over 260,000 views and 50,000 downloads, this paper highlights the industry's interest in this new approach, as everyone seeks to break through the limitations of Moore's Law.
In summary, Huawei has pointed out a new direction for the semiconductor industry: instead of constantly striving for smaller chips, we should aim for faster signal propagation. However, achieving this goal requires the joint efforts of all stakeholders in the industry.