Summary of Key Points
Advanced packaging techniques are replacing the traditional Moore's Law approach of continuously shrinking chips, becoming the foundation for the AI computing power race. As chip manufacturing processes shrink below 2nm and encounter physical limitations (such as quantum tunneling and heat dissipation issues), advanced packaging methods like Chiplet (small chip assembly) and hybrid bonding (direct copper connections) are being used to enhance performance. The market size for these technologies is expected to grow from $55 billion in 2025 to over $120 billion by 2031. TSMC leads the global AI chip packaging industry with its CoWoS technology, while domestic companies have invested heavily in expansion but still lag behind internationally in terms of technology. The Xi'an conference focused on hybrid bonding and CoPackaging Optics (CPO), providing an important insight into the future direction of these technologies.
Detailed Explanation
1. Moore's Law is No Longer Feasible; Advanced Packaging Takes Over
Over the past decade, chip performance improvements relied on shrinking transistors—each new generation doubling the number of transistors on a chip. However, at scales below 2nm, transistors approach atomic dimensions, leading to issues like quantum tunneling, increased heat dissipation, and soaring costs, making further reductions less cost-effective.
Advanced packaging approaches aim to "overtake by changing the game plan": instead of focusing on extreme miniaturization of a single chip, multiple smaller chips are combined using advanced technologies to achieve similar performance at a lower cost. According to Yole Research, advanced packaging will account for the majority of semiconductor packaging revenue by 2031 and become a critical factor in determining AI computing power, memory speed, and system costs.
2. Chiplet: Breaking Large Chips into Smaller Components for Higher Performance
Chiplet technology addresses the issue of limited chip size:
- Breaking down: A large chip is divided into smaller components (e.g., for computing, storage, and communication), each manufactured using the most suitable process to optimize costs.
- Assembling: These smaller chips are then combined using advanced packaging techniques to form a complete system. Performance depends on the communication speed and latency between the components.
- Standardization: The UCIe alliance (led by Intel and TSMC) has developed standards for chip-to-chip communication, with the 3.0 version doubling bandwidth in 2025, potentially improving performance without relying on the latest manufacturing processes. Domestic companies like Xindong Technology possess relevant intellectual property, and packaging firms like Changjiang Electronics and Tongfu are also developing related technologies.
3. Hybrid Bonding: Stronger and Faster Connections Without Solder Balls
While Chiplet focuses on how to break down chips, hybrid bonding focuses on how to assemble them more securely and efficiently:
- Traditional Methods: Chips are connected using solder balls, which are inefficient and slow.
- Hybrid Bonding: Copper pillars are used for direct connections, increasing the number of connections per unit area by 10 times (e.g., Intel's Foveros Direct 3D technology with a pitch of less than 10 microns). However, this requires precision at the nanometer level, and even a small amount of dust can ruin the process.
- Value: Hybrid bonding enhances performance and heat dissipation while saving space, making it a crucial infrastructure for AI chip competition.
4. TSMC's CoWoS: The Standard for AI Chips
TSMC's CoWoS technology is widely used in AI chips:
- Function: It integrates AI chips (e.g., NVIDIA Hopper) with high-bandwidth memory (HBM) through a silicon interlayer, meeting the demand for large amounts of fast memory.
- Capacity Constraints: Production capacity is limited; only 12K wafers can be produced per month in 2023, expected to increase to 80K by 2025. However, demand remains high, and expansion projects from TSMC and Samsung will not be available until 2027-2028, with testing capacity following a year behind.
- Supply Chain Dependency: CoWoS relies on Taiwanese manufacturers (TSMC) and Japanese suppliers (ABF substrates and T-glass), making these regions key to AI packaging.
5. Domestic Investment but Technological Gaps
Domestic companies are investing heavily in advanced packaging, but there is still a gap:
- Investment: In the first half of 2026, Changjiang Electronics, Tongfu, Huatian, and Yongxi invested a total of 27.4 billion yuan in building advanced packaging facilities for AI GPUs and Chiplet applications.
- Market Demand: Changjiang Electronics' revenue from advanced packaging accounted for nearly 70% in 2025, and Tongfu's profits increased by 224% in the first quarter of 2026, indicating strong market demand.
- Technological Gap: There is a 1-2 generation gap in sub-micron spacing and 3D stacking technologies compared to Intel's Foveros Direct 3D and TSMC's SoIC. The investment is more about closing this gap rather than immediate overtaking.
6. The Xi'an Conference: A Focus on Hybrid Bonding and CPO
The conference focused on hybrid bonding and CoPackaging Optics:
- Hybrid Bonding: Discussions centered on reducing connection pitches to sub-micron levels while maintaining high yields, which will determine future AI packaging capacity.
- CPO: This technology combines optical engines and switching chips, requiring similar precision as hybrid bonding. Domestic companies like Changjiang Electronics and Huagong Technology are already making investments in this area.
The conference highlights the simultaneous advancement of technology, production capacity, and standards, confirming the central role of advanced packaging in driving AI computing power improvements.
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